1. Field of Use
This invention pertains to data processing systems and more particularly, to register storage for the different units within such systems.
2. Prior Art
It is well known to provide scratch pad memories for storing immediate results or for storing the contents of program accessible registers (i.e., program visible registers). In systems which include more than one processing unit, it is essential that each processing unit have access to the most current version of the information stored in so-called user or program visible registers. This requirement is particularly difficult to implement in pipelined processing systems which include a succession of stages, each of which execute a different part of the instructions passed through the processor.
To meet this requirement, some systems provide a single register field memory accessible by both units. The disadvantage of this type of arrangement is that there may be significant delays incurred when the processing units are embodied in separate integrated circuit chips.
Another pipelined processor includes register file memories in two stages of the processor in which only one of the units, the execution unit, maintains the true contents of registers which are updated only as a result of instruction execution. At the completion of such execution, the updated data register contents are transferred through several register stages and buses for distribution to the register file memory of the other pipeline stage. For further information regarding this arrangement, reference may be made to U.S. Pat. No. 4,760,519 which issued on July 26, 1988.
The main disadvantage of the above arrangement is that it is not suitable for a system in which instructions are executed in an order which is different from the order in which the instructions are introduced into the pipeline. This type of system is disclosed in the related patent application of Ming-Tzer Miu and Thomas F. Joyce entitled, "Production Line Method and Apparatus for High Performance Instruction Execution." In this type of system, it is essential that each register file memory contain the same contents during any given cycle of operation or performance could be substantially affected, particularly when the units are constructed from separate integrated circuit chips.
Accordingly, it is a primary object of the present invention to provide a register file memory which can be utilized by two different units.
It is a more specific object of the present invention to provide a register file arrangement for enabling access to the most recent information by a number of units which are located on separate integrated circuit chips.